42 search results - page 8 / 9 » FPGA global routing architecture optimization using a multic... |
CCGRID
2001
IEEE
13 years 9 months ago
2001
IEEE
High performance computing on parallel architectures currently uses different approaches depending on the hardory model of the architecture, the abstraction level of the programmi...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a k...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...