134 search results - page 26 / 27 » FPGA implementation of log-polar mapping |
IOLTS
2005
IEEE
13 years 11 months ago
2005
IEEE
— In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in G...
FPL
2003
Springer
13 years 11 months ago
2003
Springer
Abstract. Data dependent circuits are logic circuits specialized to specific input data. They are smaller and faster than the original circuits, although they are not reusable and...
FCCM
2002
IEEE
13 years 10 months ago
2002
IEEE
The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing re...
FCCM
2008
IEEE
14 years 7 days ago
2008
IEEE
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
DATE
2009
IEEE
14 years 16 days ago
2009
IEEE
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...