43 search results - page 3 / 9 » Fast Inductance Extraction of Large VLSI Circuits |
HIPC
2004
Springer
13 years 10 months ago
2004
Springer
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
GLVLSI
2009
IEEE
13 years 8 months ago
2009
IEEE
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, fo...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
As the operation frequency reaches gigahertz in very deep-submicron designs, the effect of on-chip inductance on circuit performance can no longer be neglected. Therefore, it is d...