85 search results - page 1 / 17 » Fast Out-Of-Order Processor Simulation Using Memoization |
ASPLOS
1998
ACM
13 years 9 months ago
1998
ACM
Our new out-of-order processor simulator, FastSim, uses two innovations to speed up simulation 8–15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy. First...
MEMICS
2010
12 years 11 months ago
2010
Application-specific instruction set processors are the core of nowadays embedded systems. Therefore, the designers need to have powerful tools for the processor design. The tools...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of ...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
CODES
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...