6 search results - page 1 / 2 » Fast and accurate estimation of floorplans in logic high-lev... |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
ISSS
2002
IEEE
13 years 9 months ago
2002
IEEE
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...