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GLVLSI
2002
IEEE
103views VLSI» more  GLVLSI 2002»
10 years 7 months ago
Fast and accurate wire delay estimation for physical synthesis of large ASICs
Ruchir Puri, David S. Kung, Anthony D. Drumm
GLVLSI
2000
IEEE
85views VLSI» more  GLVLSI 2000»
10 years 7 months ago
Fast and accurate estimation of floorplans in logic/high-level synthesis
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
10 years 6 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
ISQED
2007
IEEE
97views Hardware» more  ISQED 2007»
10 years 9 months ago
Probabilistic Congestion Prediction with Partial Blockages
— Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing c...
Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachi...
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
10 years 8 months ago
Statistical static timing analysis using Markov chain Monte Carlo
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
Yashodhan Kanoria, Subhasish Mitra, Andrea Montana...
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