5 search results - page 1 / 1 » Fast and accurate wire delay estimation for physical synthes... |
GLVLSI
2002
IEEE
13 years 10 months ago
2002
IEEE
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
ICCAD
1991
IEEE
13 years 8 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
— Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing c...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...