10 search results - page 1 / 2 » Fast and exact transistor sizing based on iterative relaxati... |
TCAD
2002
13 years 4 months ago
2002
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...
JMLR
2010
12 years 11 months ago
2010
We propose to solve the combinatorial problem of finding the highest scoring Bayesian network structure from data. This structure learning problem can be viewed as an inference pr...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Due to the extremely large sizes of power grids, IR drop analysis has become a computationally challenging problem both in terms of runtime and memory usage. It has been shown in [...