50 search results - page 2 / 10 » Fault tolerance in cellular automata at high fault rates |
ICES
2000
Springer
13 years 8 months ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the PRPG before filling the scan chain. In this paper, we present...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
TCAD
2010
12 years 11 months ago
2010
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
NPC
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. A fault tolerant parallel virtual file system is designed and implemented to provide high I/O performance and high reliability. A queuing model is used to analyze in deta...