10 search results - page 2 / 2 » Fault-Tolerant Distributed Clock Generation in VLSI Systems-... |
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
ISPD
2006
ACM
13 years 11 months ago
2006
ACM
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
GLVLSI
2000
IEEE
13 years 10 months ago
2000
IEEE
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dualedge pulse generator and a static f...
GECCO
2009
Springer
14 years 10 days ago
2009
Springer
VLSI research, in its continuous push toward further miniaturisation, is seeking to break through the limitations of current circuit manufacture techniques by moving towards biomi...