A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladi...
We discuss the problem of concurrent error detection (CED) with bounded latency in finite state machines (FSMs). The objective of this approach is to reduce the overhead of CED, a...
We propose a number of techniques for securing finite state machines (FSMs) against fault injection attacks. The proposed security mechanisms are based on physically unclonable fun...
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...