16 search results - page 1 / 4 » Finite state machine synthesis with concurrent error detecti... |
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
DSD
2006
IEEE
13 years 7 months ago
2006
IEEE
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
We discuss the problem of concurrent error detection (CED) with bounded latency in finite state machines (FSMs). The objective of this approach is to reduce the overhead of CED, a...
ICISC
2008
13 years 6 months ago
2008
We propose a number of techniques for securing finite state machines (FSMs) against fault injection attacks. The proposed security mechanisms are based on physically unclonable fun...
ATS
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...