Sciweavers

81 search results - page 3 / 17
» Floorplanning in Modern FPGAs
Sort
View
CEE
2007
105views more  CEE 2007»
13 years 5 months ago
Compact modular exponentiation accelerator for modern FPGA devices
We present a compact FPGA implementation of a modular exponentiation accelerator suited for cryptographic applications. The implementation efficiently exploits the properties of m...
Timo Alho, Panu Hämäläinen, Marko H...
GLVLSI
2006
IEEE
165views VLSI» more  GLVLSI 2006»
13 years 12 months ago
Block alignment in 3D floorplan using layered TCG
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
13 years 11 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
FPL
2006
Springer
113views Hardware» more  FPL 2006»
13 years 9 months ago
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
Alastair M. Smith, George A. Constantinides, Peter...
ASPDAC
2006
ACM
146views Hardware» more  ASPDAC 2006»
13 years 11 months ago
A fixed-die floorplanning algorithm using an analytical approach
— Fixed-die floorplanning is an important problem in the modern physical design process. An effective floorplanning algorithm is crucial to improving both the quality and the t...
Yong Zhan, Yan Feng, Sachin S. Sapatnekar