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DAC
2007
ACM
14 years 5 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ICCD
2007
IEEE
121views Hardware» more  ICCD 2007»
14 years 1 months ago
Fast power network analysis with multiple clock domains
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transf...
Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Z...
ISPD
2005
ACM
126views Hardware» more  ISPD 2005»
13 years 10 months ago
Effects of on-chip inductance on power distribution grid
With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We pe...
Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi O...
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
13 years 10 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...
ISPD
2004
ACM
161views Hardware» more  ISPD 2004»
13 years 10 months ago
Early-stage power grid analysis for uncertain working modes
High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance ...
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar