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GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Noise tolerant low voltage XOR-XNOR for fast arithmetic
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi
TVLSI
2008
197views more  TVLSI 2008»
13 years 4 months ago
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
Behnam Amelifard, Farzan Fallah, Massoud Pedram
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 1 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
ISCAS
2006
IEEE
133views Hardware» more  ISCAS 2006»
13 years 10 months ago
Neuronal ion-channel dynamics in silicon
Abstract— We present a simple silicon circuit for modelling voltagedependent ion channels found within neural cells, capturing both the gating particle’s sigmoidal activation (...
Kai M. Hynna, Kwabena Boahen