Sciweavers

32 search results - page 3 / 7
» Fsimac: a fault simulator for asynchronous sequential circui...
Sort
View
VLSID
1997
IEEE
135views VLSI» more  VLSID 1997»
13 years 10 months ago
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxen...
DFT
2007
IEEE
104views VLSI» more  DFT 2007»
14 years 19 days ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
ICCAD
1997
IEEE
108views Hardware» more  ICCAD 1997»
13 years 10 months ago
Fault simulation of interconnect opens in digital CMOS circuits
We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...
Haluk Konuk
ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
13 years 10 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
DAC
1998
ACM
14 years 7 months ago
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, ...