174 search results - page 2 / 35 » Functional Test Generation for Full Scan Circuits |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors...
MTV
2007
IEEE
13 years 11 months ago
2007
IEEE
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
ATS
2003
IEEE
13 years 10 months ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
ISMVL
1994
IEEE
13 years 9 months ago
1994
IEEE