82 search results - page 2 / 17 » Functional Testing of Microprocessors with Graded Fault Cove... |
VTS
2000
IEEE
13 years 9 months ago
2000
IEEE
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulate...
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
VTS
2000
IEEE
13 years 9 months ago
2000
IEEE
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...