171 search results - page 2 / 35 » Future Performance Challenges in Nanometer Design |
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...
TVLSI
2008
13 years 4 months ago
2008
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, u...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...