694 search results - page 1 / 139 » Gate Sizing Using a Statistical Delay Model |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper is about gate sizing under a statistical delay model. It shows we can solve the gate sizing problem exactly for a given statistical delay model. The formulation used al...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...