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13

DATE
2000
IEEE

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Gate Sizing Using a Statistical Delay Model

13 years 9 months ago

Gate Sizing Using a Statistical Delay Model

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This paper is about gate sizing under a statistical delay model. It shows we can solve the gate sizing problem exactly for a given statistical delay model. The formulation used allows many different forms of objective functions, which could for example directly optimize the delay uncertainty at the circuit outputs. We formulate the gate sizing problem as a nonlinear programming problem, and show that if we do this carefully, we can solve these problems exactly for circuits up to a few thousand gates using the publicly available large scale nonlinear programming solver LANCELOT.

E. T. A. F. Jacobs, Michel R. C. M. Berkelaar

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DATE 2000 | Gate Sizing Problem | Hardware | Sizing | Statistical Delay Model |

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Added	30 Jul 2010
Updated	30 Jul 2010
Type	Conference
Year	2000
Where	DATE
Authors	E. T. A. F. Jacobs, Michel R. C. M. Berkelaar

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