694 search results - page 2 / 139 » Gate Sizing Using a Statistical Delay Model |
PATMOS
2007
Springer
13 years 11 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
TCAD
2008
13 years 5 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
DAC
1995
ACM
13 years 9 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...