24 search results - page 5 / 5 » Gated Clock Routing Minimizing the Switched Capacitance |
SLIP
2004
ACM
13 years 10 months ago
2004
ACM
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the...
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
ISPD
2005
ACM
13 years 11 months ago
2005
ACM
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. With thes...