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IPPS
2006
IEEE
13 years 10 months ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
ASAP
2008
IEEE
110views Hardware» more  ASAP 2008»
13 years 11 months ago
Design space exploration of a cooperative MIMO receiver for reconfigurable architectures
Cooperative MIMO is a new technique that allows disjoint wireless communication nodes (e.g. wireless sensors) to form a virtual antenna array to increase bandwidth, reliability an...
Shahnam Mirzaei, Ali Irturk, Ryan Kastner, Brad T....
FPL
2009
Springer
145views Hardware» more  FPL 2009»
13 years 9 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
13 years 10 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...