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ISQED
2006
IEEE
116views Hardware» more  ISQED 2006»
14 years 2 days ago
Probabilistic Delay Budgeting for Soft Realtime Applications
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
Soheil Ghiasi, Po-Kuan Huang
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 1 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
14 years 3 months ago
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
Krishnan Srinivasan, Karam S. Chatha, Goran Konjev...
DATE
2000
IEEE
105views Hardware» more  DATE 2000»
13 years 10 months ago
System Synthesis for Multiprocessor Embedded Applications
This paper presents the system synthesis techniques available in S3 E2 S, a CAD environment for the specification, simulation, and synthesis of embedded electronic systems that ca...
Luigi Carro, Márcio Eduardo Kreutz, Fl&aacu...
FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
13 years 7 months ago
Pattern-based behavior synthesis for FPGA resource reduction
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
Jason Cong, Wei Jiang