188 search results - page 1 / 38 » Guiding Architectural SRAM Models |
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...