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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 1 months ago
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
Ansgar Stammermann, Domenik Helms, Milan Schulte, ...
DAC
1999
ACM
13 years 9 months ago
Common-Case Computation: A High-Level Technique for Power and Performance Optimization
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed ...
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S...
DATE
2005
IEEE
91views Hardware» more  DATE 2005»
13 years 10 months ago
Reliability-Centric High-Level Synthesis
Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density c...
Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, ...
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
14 years 1 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
VLSI
2005
Springer
13 years 10 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...