112 search results - page 1 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
MEMOCODE
2007
IEEE
13 years 11 months ago
2007
IEEE
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
ASAP
2006
IEEE
13 years 8 months ago
2006
IEEE
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The pr...
FPT
2005
IEEE
13 years 10 months ago
2005
IEEE
The performance of security applications can be greatly improved by accelerating the cryptographic algorithms in hardware. In this paper, an implementation of the Secure Shell (SS...