Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

9

MEMOCODE
2007
IEEE

favoriteEmaildiscussreport

115views Formal Methods» more MEMOCODE 2007»

Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA

13 years 10 months ago

Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA

Download csg.csail.mit.edu

Nirav Dave, Kermin Fleming, Myron King, Michael Pe

Real-time Traffic

MEMOCODE 2007 |

claim paper

Related Content

» 64bit floatingpoint FPGA matrix multiplication

» Accelerating FPGAbased emulation of quasicyclic LDPC codes with vector processing

» Reconfigurable Fixed Point Dense and Sparse MatrixVector MultiplyAdd Unit

» HardwareAccelerated SSH on SelfReconfigurable Systems

» FPGA Implementation of a Maze Routing Accelerator

» Configuration Compression for the Xilinx XC6200 FPGA

» Sparse MatrixVector multiplication on FPGAs

» An FPGA Network Architecture for Accelerating 3DES CBC

» Hardware acceleration of multiview face detection

Post Info
More Details (n/a)

Added	04 Jun 2010
Updated	04 Jun 2010
Type	Conference
Year	2007
Where	MEMOCODE
Authors	Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan

Comments (0)