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» Hardware synchronization for embedded multi-core processors
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ASYNC
1998
IEEE
122views Hardware» more  ASYNC 1998»
13 years 9 months ago
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
Martin Benes, Steven M. Nowick, Andrew Wolfe
FPL
2006
Springer
242views Hardware» more  FPL 2006»
13 years 8 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
MAM
2006
126views more  MAM 2006»
13 years 4 months ago
HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems
Embedded systems are typically heterogeneous requiring interacting hardware and software components, are locally synchronous while being globally asynchronous and combine both con...
Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza...
DATE
2009
IEEE
151views Hardware» more  DATE 2009»
13 years 11 months ago
pTest: An adaptive testing tool for concurrent software on embedded multicore processors
—More and more processor manufacturers have launched embedded multicore processors for consumer electronics products because such processors provide high performance and low powe...
Shou-Wei Chang, Kun-Yuan Hsieh, Jenq Kuen Lee
SAMOS
2004
Springer
13 years 10 months ago
Synchronous Transfer Architecture (STA)
This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and ...
Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil...