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» Hazard Checking of Timed Asynchronous Circuits Revisited
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ACSD
2007
IEEE
67views Hardware» more  ACSD 2007»
13 years 11 months ago
Hazard Checking of Timed Asynchronous Circuits Revisited
This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from statespace explosion...
Frédéric Béal, Tomohiro Yoned...
ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
14 years 2 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
SRDS
1997
IEEE
13 years 9 months ago
Software Approach to Hazard Detection Using On-line Analysis of Safety Constraints
Hazard situations in safety-critical systems are typically complex, so there is a need for means to detect complex hazards and react in a timely and meaningful way. This paper add...
Beth A. Schroeder, Karsten Schwan, Sudhir Aggarwal
ICCAD
1999
IEEE
125views Hardware» more  ICCAD 1999»
13 years 9 months ago
Direct synthesis of timed asynchronous circuits
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
Sung Tae Jung, Chris J. Myers
ATS
2001
IEEE
101views Hardware» more  ATS 2001»
13 years 9 months ago
Framework of Timed Trace Theoretic Verification Revisited
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or...
Bin Zhou, Tomohiro Yoneda, Chris J. Myers