Sciweavers

Share
ATS
2001
IEEE

Framework of Timed Trace Theoretic Verification Revisited

9 years 5 months ago
Framework of Timed Trace Theoretic Verification Revisited
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.
Bin Zhou, Tomohiro Yoneda, Chris J. Myers
Added 23 Aug 2010
Updated 23 Aug 2010
Type Conference
Year 2001
Where ATS
Authors Bin Zhou, Tomohiro Yoneda, Chris J. Myers
Comments (0)
books