7 search results - page 1 / 2 » Hierarchical Error Diagnosis Targeting RTL Circuits |
VLSID
2000
IEEE
13 years 9 months ago
2000
IEEE
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
ATS
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
VTS
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
Commonly used pattern sources in simulation-based verification include random, guided random, or design verification patterns. Although these patterns may help bring the design ...