238 search results - page 1 / 48 » Hierarchical Interconnect Circuit Models |
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order re...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...