31 search results - page 5 / 7 » High Level Synthesis of Pipelined Instruction Set Processors... |
ICCD
2005
IEEE
13 years 11 months ago
2005
IEEE
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
SAC
2006
ACM
13 years 11 months ago
2006
ACM
Esterel is a concurrent synchronous language for developing reactive systems. As an alternative to the classical software and hardware synthesis paths, the reactive processing app...
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
CASES
2006
ACM
13 years 11 months ago
2006
ACM
Embedded application requirements, including high performance, low power consumption and fast time to market, are uncommon in the broader domain of general purpose applications. I...