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» High-Level Power Modeling, Estimation, and Optimization
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IPPS
2006
IEEE
14 years 2 days ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 10 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
14 years 2 months ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
14 years 3 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
DATE
2002
IEEE
101views Hardware» more  DATE 2002»
13 years 11 months ago
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization
This paper presents a novel Energy-Aware Compilation (EAC) framework that can estimate and optimize energy consumption of a given code taking as input the architectural and techno...
Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vija...