24 search results - page 1 / 5 » High-speed VLSI architecture for parallel Reed-Solomon decod... |
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
FCCM
2004
IEEE
13 years 8 months ago
2004
IEEE
We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision ReedSolomon decoding algorithm. The key feature is the embedding of b...
GLVLSI
1996
IEEE
13 years 9 months ago
1996
IEEE
FPGA
2006
ACM
13 years 8 months ago
2006
ACM
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
DFT
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper, a simple codec algorithm based on Reed-Solomon (RS) codes is proposed for erasure correcting in RAID (Redundant Array of Independent Disks) level 6 systems. Unlike ...