4 search results - page 1 / 1 » Impact of interconnect variations on the clock skew of a gig... |
DAC
2000
ACM
14 years 5 months ago
2000
ACM
Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors c...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Under modern VLSI technology, process variations greatly affect circuit performance, especially clock skew which is very timing sensitive. Unwanted skew due to process variation f...
DAC
2007
ACM
13 years 8 months ago
2007
ACM
With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated ...
INTEGRATION
2008
13 years 4 months ago
2008
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non...