Sciweavers

164 search results - page 3 / 33
» Implementing and Evaluating Stream Applications on the Dynam...
Sort
View
CODES
2009
IEEE
13 years 10 months ago
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators
Reconfigurable Processors utilize a reconfigurable fabric (to implement application-specific accelerators) and may perform runtime reconfigurations to exchange the set of deployed...
Lars Bauer, Muhammad Shafique, Jörg Henkel
FPL
2008
Springer
129views Hardware» more  FPL 2008»
13 years 7 months ago
Power reduction techniques for Dynamically Reconfigurable Processor Arrays
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito,...
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
13 years 9 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
13 years 11 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...
EH
1999
IEEE
122views Hardware» more  EH 1999»
13 years 10 months ago
The MorphoSys Dynamically Reconfigurable System-on-Chip
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Ba...