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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 2 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
CHES
2005
Springer
82views Cryptology» more  CHES 2005»
13 years 11 months ago
Masking at Gate Level in the Presence of Glitches
Abstract. It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by “secure” random masking schemes, leak side-cha...
Wieland Fischer, Berndt M. Gammel
RTAS
2005
IEEE
13 years 11 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
RAS
2008
80views more  RAS 2008»
13 years 4 months ago
Motion design and learning of autonomous robots based on primitives and heuristic cost-to-go
The task of trajectory design of autonomous vehicles is typically two-fold. First, it needs to take into account the intrinsic dynamics of the vehicle, which are sometimes termed ...
Keyong Li, Raffaello D'Andrea