34 search results - page 6 / 7 » Improved Effective Capacitance Computations for Use in Logic... |
DATE
2009
IEEE
14 years 9 days ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
ICPP
1998
IEEE
13 years 9 months ago
1998
IEEE
Many large scale applications, have significant I/O requirements as well as computational and memory requirements. Unfortunately, limited number of I/O nodes provided by the conte...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
We discuss the use of convolutional codes to perform concurrent error detection (CED) in finite state machines (FSMs). We examine a previously proposed methodology, we identify i...