12 search results - page 1 / 3 » Improved on-chip router analytical power and area modeling |
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
ASPDAC
2010
ACM
13 years 2 months ago
2010
ACM
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
NOCS
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
GLOBECOM
2007
IEEE
13 years 11 months ago
2007
IEEE
—The growth of the Internet in the last years has been pushed by increasing requirements in terms of capacity, security and reliability. Moreover, improvements in multimedia appl...