328 search results - page 2 / 66 » Improving Performance of Small On-Chip Instruction Caches |
EUROPAR
2003
Springer
13 years 10 months ago
2003
Springer
As compared to a complex single processor based system, on-chip multiprocessors are less complex, more power efficient, and easier to test and validate. In this work, we focus on a...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
EUROPAR
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
ASAP
2005
IEEE
13 years 11 months ago
2005
IEEE
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
MICRO
2007
IEEE
13 years 11 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...