11 search results - page 1 / 3 » Improving soft-error tolerance of FPGA configuration bits |
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped...
HPCA
2009
IEEE
13 years 11 months ago
2009
IEEE
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...