25 search results - page 2 / 5 » Increasing Processor Performance Through Early Register Rele... |
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission ...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
DSN
2005
IEEE
13 years 11 months ago
2005
IEEE
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
PACS
2004
Springer
13 years 10 months ago
2004
Springer
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...