Sciweavers

20 search results - page 1 / 4
» Instruction Encoding Techniques for Area Minimization of Ins...
Sort
View
ISSS
1998
IEEE
87views Hardware» more  ISSS 1998»
13 years 9 months ago
Instruction Encoding Techniques for Area Minimization of Instruction ROM
In this paper, we propose instruction encoding techniques for embedded system design, which encode immediate fields of instructions to reduce the size of an instruction memory. Al...
Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, ...
JCP
2008
118views more  JCP 2008»
13 years 4 months ago
Power-efficient Instruction Encoding Optimization for Various Architecture Classes
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
Diandian Zhang, Anupam Chattopadhyay, David Kammle...
CODES
2006
IEEE
13 years 8 months ago
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 9 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
HIPC
2000
Springer
13 years 8 months ago
Improving Offset Assignment on Embedded Processors Using Transformations
Embedded systems consisting of the application program ROM, RAM, the embedded processor core and any custom hardware on a single wafer are becoming increasingly common in areas suc...
Sunil Atri, J. Ramanujam, Mahmut T. Kandemir