154 search results - page 3 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
FCCM
2005
IEEE
13 years 11 months ago
2005
IEEE
FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose processors. Inability t...
ARVLSI
2001
IEEE
13 years 9 months ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...