12 search results - page 2 / 3 » Interconnect delay minimization through interlayer via place... |
GLVLSI
2006
IEEE
14 years 6 days ago
2006
IEEE
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
SLIP
2009
ACM
14 years 20 days ago
2009
ACM
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
3DIC
2009
IEEE
14 years 29 days ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
ICCD
2007
IEEE
14 years 3 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
ASPDAC
2011
ACM
12 years 9 months ago
2011
ACM
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...