24 search results - page 4 / 5 » Interface timing verification with delay correlation using c... |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
CADE
2002
Springer
14 years 6 months ago
2002
Springer
Abstract. We investigate the combination of propositional SAT checkers with domain-specific theorem provers as a foundation for bounded model checking over infinite domains. Given ...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a technique for memory optimization for a class of computations that arises in the field of correlated electronic structure methods such as coupled cluster and...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...