14 search results - page 1 / 3 » Interrupt modeling for efficient high-level scheduler design... |
TODAES
2008
13 years 5 months ago
2008
VLSID
2009
IEEE
14 years 6 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
CODES
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
EUROMICRO
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constra...