16 search results - page 2 / 4 » Joint Minimization of Power and Area in Scan Testing by Scan... |
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
ATS
2005
IEEE
13 years 10 months ago
2005
IEEE
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...