6 search results - page 1 / 2 » Layout Compaction for Yield Optimization via Critical Area M... |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents a new compaction algorithm to improve the yield of IC layout. The yield is improved by reducing the area where the faults are more likely to happen known as cr...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
— Chemical-Mechanical Polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This pap...
DATE
2009
IEEE
13 years 8 months ago
2009
IEEE
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...